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PTP OC/TC Measurement results

Sunday, April 30, 2017 - 14:57

The hardware-only implementations of the PTP Ordinary Clock (OC) and Transparent Clock (TC) were assesed according to the IEEE C37.238 Standard. The quantitative data shows exceptional performance of the offered implementations even in high load Ethernet networks. The available accuracy and precision budgets exceed the overall functional requirements of the e.g. smart grid applications by an order of magnitude in the tested situations. [more...]

HSR/PRP-Core Version 2.4.003 Release

Tuesday, February 14, 2017 - 19:35

The current release extends the HSR/PRP core with the Doubly Attached Clock (DAC) functionality according to IEC 62439-3:2016 standard. The DAC ensures reliable time synchronization of the local clock over two redundant paths and supports Layer-2 Peer-To-Peer Precision Time Protocol. The DAC is hardware-only implementation with small resource footprint and requires no dedicated PTP software stack.

ISPCS 2016 Plugfest and Symposium

Monday, June 20, 2016 - 10:28

VeryLogic GmbH participates this year‘s ISPCS 2016 Plugfest and Symposium. We are going to demonstrate the performance and interoperability of the HSR/PRP/SLTC-Core and the new 1588v2 OrdinaryClock. Meet us and get a live-demonstration of our products. We look forward to your visit!

HSR/PRP-Core Version 2.3 Release

Monday, October 26, 2015 - 11:13

The HSR/PRP-Core version 2.3 was successfully released. It features an optional, one-step Stateless Transparent Clock (SLTC) implementation compliant to IEEE 1588v2 standard. The new SLTC supports time synchronization according to Peer-to-peer (P2P) protocol in industrial Ethernet networks.

HSR/PRP-Core Version 2.02 Release

Thursday, July 16, 2015 - 21:35

The HSR/PRP-Core version 2.02 was successfully released. It features numerous 32-bit wide Interfaces Status Counters, which are a superset of already implemented Monitoring Data Set.

HSR/PRP-Core Version 2.01 Release

Wednesday, June 17, 2015 - 21:38

The HSR/PRP-Core version 2.01 was successfully released. It features segmented Frame Buffers with logical Priority Queues with up to 8-VLAN based frame priority levels. Furthermore all (R)(G)MII interface styles for external MAC- and PHY-device interconnect are directly supported.

HSR-Core release

Thursday, November 20, 2014 - 13:05

The new HSR-Core was successfully tested and its first version was released. The HSR-Core uses the same code base as the existing PRP-Core and features very low resource usage in contrast to other implementations.

Homepage launch

Monday, July 14, 2014 - 20:00

The homepage of VeryLogic GmbH was successfully launched.